Custom Multi Capacitor Array 4 Channel 100pF 30V MOS Capacitor 100 Percent Wafer Level Tested SLC Chip

HACC-100S30V100 Custom Multi-Capacitor Array MOS Chip 4 Channel * 100pF 30V Wafer-Level Tested Verified Low Defect Rate

The HACC-100S30V100 is a fully customizable single-layer MOS multi-capacitor array integrating four independent 100pF ±10% capacitor blocks on a single 1.00 * 1.00 * 0.15mm die. Each channel features its own top electrode bond pad with independent wire-bond access, while all channels share a common backside ground plane through TiW-Pt-Au metallization. Fabricated on high-resistivity float-zone silicon (>1000 Ω·cm) with 300nm thermal SiO₂ dielectric, this array replaces four discrete single-layer capacitors with a single chip — reducing assembly steps, bond wire count, and hybrid circuit footprint by up to 75%. Every die undergoes 100% wafer-level DC and RF parametric testing with verified defect rate below 10 DPPM through 2 million device-hour accelerated life testing per JEDEC JESD74A, with SPC-controlled process capability (CpK >1.67).

1. Customizable Multi-Capacitor Arrays — One Chip, Multiple Values

The HACC-ARRAY4-100S30V100 integrates four independent capacitor blocks in a single die, each individually wire-bondable. This architecture delivers three fundamental advantages over discrete multi-chip solutions:

• 75% assembly footprint reduction: Four discrete 0.50mm chips require approximately 1.75mm² of carrier area including placement spacing. The HACC-ARRAY4 integrates all four capacitors into a single 1.00mm² die — a 43% area reduction — while eliminating three die-attach steps, three placement operations, and three separate inspections.
• Matched temperature coefficient across all channels: Because all four capacitor blocks share the same silicon substrate and the same SiO₂ dielectric thermal oxidation process, the TCC of 0 ±30 ppm/°C is matched to within ±1% channel-to-channel within-die. This eliminates the TCC mismatch that inevitably arises when four discrete capacitors from different wafer positions (or different wafer lots) are used in a phased-array or multi-channel application.
• Reduced bond wire inductance: With a single shared backside ground connection, the common ground return path eliminates the cumulative ground inductance of four discrete capacitors. Each channel maintains its own <0.05nH intrinsic ESL, and the shared backside minimizes ground loop area for parallel-connected configurations.

2. Configurable Array Architecture — Standard and Custom Layouts

The HACC-ARRAY4 platform supports multiple array configurations to match your specific circuit topology:

• 4-Channel Equal-Value Array (standard): Four independent 100pF blocks on a 1.00mm square die. Each block has its own top electrode pad (200 * 200µm) spaced with >150µm pad-to-pad pitch for compatible automated bonding. Ideal for 4-channel phased-array beamformer DC blocking, 4-lane SERDES coupling, and multi-channel TIA bias filtering.
• Binary-Weighted Array (1:2:4:8): Four blocks with capacitance ratios of 1:2:4:8 (e.g., 50pF : 100pF : 200pF : 400pF). By selectively wire-bonding combinations of channels, the designer can realize 15 discrete capacitance values from a single die — replacing an entire capacitor bank with one component. Ideal for precision tuning networks and reconfigurable matching circuits.
• Custom Channel Count (2–8 blocks): Arrays from 2 to 8 independent channels, each with customer-specified capacitance from 5pF to 1000pF. Custom die geometries — rectangular aspect ratios up to 4:1, L-shape, or annular layouts — accommodate non-standard hybrid circuit footprints.

3. Wafer-Level Testing — 100% Parametric Coverage per Channel

Every HACC-ARRAY4 die undergoes 100% wafer-level DC and RF testing before dicing. The test program covers every capacitor channel on every die — not a sample-based AQL approach:

• DC parametric test per channel: Capacitance at 1MHz/1.0Vrms (±10% spec limit), leakage current at rated 30V DC (<10nA spec limit), and dielectric withstanding voltage (>75V, 5-second dwell). Each channel is individually probed and measured.
• Channel-to-channel matching verification: Capacitance mismatch between any two channels on the same die is verified <±1%. Dies exceeding this limit are inked for exclusion.
• Channel-to-channel isolation: Isolation resistance >10¹⁰ Ω between adjacent channels at 30V DC, with coupling capacitance <0.05pF. This ensures that RF signals on one channel do not cross-couple to adjacent channels through the substrate.
• Digital wafer map: Every die is binned by capacitance value, leakage, and channel matching grade. The XML KRF-format wafer map enables automated die sorting by bin code and provides full known-good-die (KGD) traceability for each shipped lot.

4. Verified Low Defect Rate — Verified Through Accelerated Life Testing

A defect rate below 10 DPPM (Defective Parts Per Million) is not an aspirational goal — it is a verified production metric supported by the following quality infrastructure:

• 2 million device-hour accelerated life test: Per JEDEC JESD74A, production samples are subjected to 125°C / 85% RH / 30V DC bias for 1000 hours (equivalent to >10 years field life at 55°C / 60% RH per Arrhenius-Peck acceleration model). Zero failures observed across the qualification sample set, yielding a demonstrated defect rate below 10 DPPM at 60% confidence.
• 100% wafer-level probe with inkless binning: Every capacitor site on every wafer is probed. Out-of-specification die are electronically mapped rather than physically inked, eliminating ink particle contamination risk in the cleanroom environment. The wafer map is transferred directly to the automated pick-and-place die sorter.
• SPC-controlled process with CpK >2.0: Capacitance, leakage, and breakdown voltage are monitored per wafer lot using statistical process control (SPC) charts. Process capability index (CpK) exceeds 2.0 for all critical parameters, providing substantial margin beyond the verified defect rate claim.
• Closed-loop corrective action: Any parametric shift exceeding 1.5σ from the process mean triggers an automated lot hold and root-cause investigation, preventing out-of-trend material from shipping regardless of whether individual die meet specification limits.

5. Electrical Specifications (T = 25°C unless noted)

6. Assembly Quick Reference

• Die Attach: AuSn eutectic solder (300–320°C, N₂/H₂) or conductive Ag epoxy (Epotek H20E, 120°C/30min). Single die-attach step replaces four discrete placements.
• Wire Bonding per Channel: 25µm Au thermosonic ball bonding (120–150°C stage, >6gf pull strength). Each of the four channels has its own 200*200µm pad with >150µm pitch — compatible with automated sequential bonding. For parallel-connected channels, bond multiple pads to a common node.
• Storage: Waffle pack with KGD wafer map, vacuum-sealed nitrogen purge. MSL 1 unlimited floor life. Store at 20–25°C, 40–60% RH.

7. Typical Applications

• Phased-Array Beamformer T/R Modules: Four matched 100pF DC blocking capacitors in a single die, with channel-to-channel TCC matching and capacitance uniformity <±1% — critical for per-element amplitude and phase tracking across the array aperture.
• Multi-Channel SERDES (56/112 Gbps PAM4): Four independent DC blocking channels for 4-lane transmit or receive paths, replacing four discrete capacitors with one component and reducing assembly complexity in high-density optical module interposers.
• Multi-Band Tunable Matching Networks: Binary-weighted array (1:2:4:8) provides 15 selectable capacitance combinations through selective wire bonding — enabling post-assembly impedance tuning without component replacement.
• Satellite Communication Multi-Channel Downconverters: Sub-PPM defect rate and 100% wafer-level testing per ESCC qualification standards provide the reliability required for LEO/MEO constellation payloads with 10–15 year mission life.
• Automated Test Equipment (ATE) Pin Electronics: Four matched bypass capacitors per pin electronics channel in a single chip, with KGD wafer map traceability supporting ISO 17025 calibration requirements.

8. Ordering and Custom Configuration

Standard product ships as the HACC-100S30V100: 4-channel, 100pF per channel, 30V, 1.00 * 1.00mm die in waffle pack with KGD wafer map. Custom configurations available on request with minimum order quantities starting at 100 pieces:

• Channel count: 2, 3, 4, 6, or 8 independent channels
• Capacitance per channel: 5pF to 1000pF (any value, any combination)
• Array topology: Equal-value, binary-weighted (1:2:4:8), or arbitrary custom ratios
• Die geometry: Standard square or custom rectangular/asymmetric outlines to fit existing hybrid circuit layouts
• Voltage rating: 6.3V to 100V DC
• Delivery format: Waffle pack, gel-pak, or tape-and-reel

Contact us with your array requirements for a feasibility assessment, lead time estimate, and quotation. Standard 4-channel 100pF evaluation samples ship within 3–4 weeks with full per-channel parametric test data, channel matching reports, and digital KGD wafer map.

4 channel MOS capacitor array

100pF 30V MOS capacitor

wafer level tested SLC chip

Custom Multi Capacitor Array 4 Channel 100pF 30V MOS Capacitor 100 Percent Wafer Level Tested SLC Chip Images